MATRIX16: A 16-Channel Low-Power TDC ASIC with 8 ps Time Resolution

This paper presents a highly configurable 16-channel TDC ASIC designed in commercial 180 nm technology with the following features: time-of-flight and time-over-threshold measurements, 8.6 ps LSB, 7.7 jitter, 5.6 linearity error, up to 5 MHz of sustained input rate per channel, 9.1 mW power consumption an area 4.57 mm2. The main contributions this work are novel design clock interpolation circuitry based on resistive mesh circuit capability operate at different supply voltages operating frequencies, thus providing compromise between resolution consumption.